The present invention relates to a technique which is especially effective when applied to a data reading system for a semiconductor memory device and, more particularly, to a technique which is effective when applied to a nonvolatile memory device (as will be simply referred to as the "flash memory") capable of erasing the data stored in a plurality of nonvolatile memory cells, electrically simultaneously.
In a highly integrated semiconductor memory, such as a dynamic random access memory (DRAM), one of the techniques, which has been adapted to prevent power noise caused at the start of operation of a sense amplifier, is one in which a current source for the sense amplifier is constructed to include a pair of MOSFETs connected in parallel and having different channel lengths. At the time of drive of the sense amplifier, one (i.e., the MOSFET having a smaller channel length) of the paired MOSFETs is turned on at first, and the other MOSFET (i.e., the MOSFET having a larger channel length) is then turned on. This effectively reduces the power fluctuation caused at the start of operation of the sense amplifier and reduces the noise due to power fluctuation, thereby to reduce erroneous reading of the DRAM. One of the publications disclosing the aforementioned techniques is Japanese Patent Laid-Open No. 62-275385 (275385/1983).
In the DRAM, the open bit line system having a low noise resistance has been adopted at first, but this system has been replaced by the folded bit line system, which has an excellent noise resistance. When noise occurs in the memory array of the DRAM of this folded bit line system, in-phase noise is transmitted to a pair of bit lines connected with one CMOS latch type differential sense amplifier through a parasitic capacitance between the bit lines. The differential sense amplifier is insensitive to the in-phase noise component on the paired bit lines so that the potential change of the bit lines in response to the data stored in a selected memory cell is accurately detected by the differential amplifier even if the in-phase noise component is carried on the paired bit lines.
A bit line shield system is a known technique for preventing erroneous reading of data due to noise in the semiconductor memory of the open bit line system. In the bit line shield system, in order to prevent erroneous reading of data due to the transmission of noise through the parasitic capacitance between adjoining data lines, the data lines are selected alternately every other line at the data reading time, and the unselected data lines are fixed at a ground potential or a reference potential. As a result, the unselected data lines, set to the ground potential or the reference potential, function as shielded lines to prevent erroneous reading of data.
In recent years, meanwhile, the simultaneous erase type electrically erasable and programmable nonvolatile read only memory (also referred to as the "flash EEPROM" or the "flash memory") is one of the nonvolatile memories which as been used as a memory medium for a portable personal computer, a portable telephone, a digital still camera or a flash memory card, and investigations and developments have been made for manufacturing a flash memory and for making a flash memory multivalue system.
In the flash memory, too, the open bit line system and the folded bit line system are employed. Examples of flash memories of the open bit system or the folded bit line system are disclosed in Japanese Patent Laid-Open Nos. 7-153286 (153286/1995), 7-57482 (57482/1995) corresponding to U.S. Pat. No. 5,446,690 and 9-35486 (35486/1997).
Meanwhile, a flash memory adopting the open bit line system and the bit line shielded system is disclosed in Japanese Patent Laid-Open No. 7-45087 (45087/1995) corresponding to U.S. Pat. No. 5,473,570.